Herb Sutter gave an interesting talk titled Machine Architecture: Things Your Programming Language Never Told You:

In it he gives a tiny yet very interesting example of code that illustrates hardware destructive interference: how the size of L1 cache line and improper data layout can negatively affect performance of your code.
The example program allocates two int’s on the heap one right next to the other. It then starts two threads; each thread reads and writes to one of the int’s location. Let’s do just that, 100’000’000 times and see how long it takes:

Duration: 4338.55 ms

Let us now do the same exact thing, except this time we’ll space the int’s apart, by… you guessed it, L1 cache line size (64 bytes on Intel and AMD x64 chips):

Duration: 1219.50 ms

The same code now runs 4 times faster. What happens is that the L1 caches of the CPU cores no longer have to be synchronized every time we write to a memory location.

Lesson here is that data layout in memory matters. If you must run multiple threads that perform work and write to memory locations, make sure those memory locations are separated by L1 cache line size. C++17 helps us with that: Hardware Constructive and Destructive Interference Size.

Complete listing:

6 Replies to “L1 cache lines”

  1. I can reproduce your numbers in debug mode, but in release mode the difference is much smaller.

    Debug
    ~270 ms – CACHE_LINE_SIZE = 64;
    ~630 ms – CACHE_LINE_SIZE = sizeof(int);

    Release
    ~240 ms – CACHE_LINE_SIZE = 64;
    ~270 ms – CACHE_LINE_SIZE = sizeof(int);

    Compiled on a Lenovo with VS2017 on an Windows 7 64 bit i7-3720QM @ 2.6 GHz

    Any idea why?

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